RELEASED
PM7350 S/UNI DUPLEX
DATA SHEET
PMC-1980581
ISSUE 8
DUAL SERIAL LINK PHY MULTIPLEXER
DDSCR:
The DDSCR bit controls the descrambling of the cell payload with the
polynomial x43 + 1. When DDSCR is set to logic 1, cell payload descrambling
is disabled. When DDSCR is set to logic 0, payload descrambling is enabled.
IDLEPASS:
The IDLEPASS bit controls the function of the idle cell filter. When IDLEPASS
is written with a logic 0, all idle cells (first four bytes of cell are ‘H00, ‘H00,
‘H00, ‘H01) are filtered out. When IDLEPASS is logic 1, idle cells are passed
on to the cell buffer.
UNASSPASS:
When UNASSPASS is written with a logic 0, all unassigned cells (first four
bytes of cell are ‘H00, ‘H00, ‘H00, ‘H00) are filtered out. When UNASSPASS
is logic 1, unassigned cells are passed on the cell buffer.
HCSPASS:
The HCSPASS bit controls the dropping of cells based on the detection of an
HCS error. When HCSPASS is logic 0, cells containing an HCS error are
dropped. When HCSPASS is a logic 1, cells are passed to the external cell
buffer regardless of errors detected in the HCS. Regardless of the
programming of this bit, cells are always dropped while the cell delineation
state machine is in the 'HUNT' or 'PRESYNC' states.
PROV:
The indirect provision enable bit (PROV) reports the channel provision enable
flag read from the channel provision RAM after an indirect channel read
operation has completed. When PROV is set to logic 1, the TC processor will
process data on the channel specified by CHAN[3:0]. When PROV is set to
logic 0, the TC processor will ignore data on the channel specified by
CHAN[3:0].
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
162
PMC [ PMC-SIERRA, INC ]
