S/UNI-IMA-4 Telecom Standard Product Data Sheet
Released
10.7.3 Registers
The Register Memory Map in Table 5 shows where the normal mode registers are accessed. The
resulting register organization is split into sections: Master configuration registers, TC Layer,
Clock/Data Interface and IMA Sublayer registers.
On power up, the S/UNI-IMA-4 requires configuration. For proper operation, register
configuration is necessary in order to program addresses for the Any-PHY ports, enable the
SDRAM, configure the Line interface and chose IMA or TC mode for each link/group. By
default, interrupts will not be enabled.
The Line-side-access defaults to a disabled state; this results in all line side output pins being
tristated. When the Clock/Data line mode is chosen, the pins will be enabled.
Table 5 Register Memory Map
Address
Register
0x000 –
Master Configuration and Interrupts
0x05E
0x000
Global Reset
0x002
Global Configuration
0x004
JTAG ID (MSB)
0x006
JTAG ID (LSB)
0x008
Master Interrupt Register
0x00A
0x00C
0x00E
0x010
0x012
0x014
0x016-0x01E
0x020
0x022
0x024
0x026
Miscellaneous Interrupt Register
RTTC Interrupt FIFO
Reserved
Master Interrupt Enable Register
Miscellaneous Interrupt Enable Register
TC Interrupt Enable Register
Reserved
Transmit Any-PHY/UTOPIA Cell Available Enable
Receive UTOPIA Cell Available Enable
Receive Any-PHY/UTOPIA Config Register (RXAPS_CFG)
Transmit Any-PHY/UTOPIA Config Register (TXAPS_CFG)
Transmit Any-PHY Address Config Register (TXAPS_ADD_CFG)
Reserved
0x028
0x02A-0x03E
0x040
SDRAM Configuration
0x042
SDRAM Diagnostics
0x044
0x046
0x048
0x04A
SDRAM Diag Burst RAM Indirect Access
SDRAM Diag Indirect Burst Ram Data LSB
SDRAM Diag Indirect Burst Ram Data MSB
SDRAM DIAG WRITE CMD 1
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2020889, Issue 2
93
PMC [ PMC-SIERRA, INC ]
