S/UNI-IMA-4 Telecom Standard Product Data Sheet
Released
RESET
The RESET bit implements a software reset for the entire S/UNI-IMA-4. If the RESET bit
is a logic 1, the entire S/UNI-IMA-4 is held in reset except for the microprocessor interface.
While in reset, the only register that is accessible is the Global Reset register. This bit is not
self-clearing; therefore, a logic 0 must be written to bring the S/UNI-IMA-4 out of reset.
Holding the S/UNI-IMA-4 in a reset state effectively puts it into a low power, stand-by
mode. A hardware reset sets the RESET bit, thus asserting the software reset.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2020889, Issue 2
97
PMC [ PMC-SIERRA, INC ]
