S/UNI-IMA-4 Telecom Standard Product Data Sheet
Released
10.7 Microprocessor Interface
The Microprocessor Interface Block provides the interrupt logic and an interface to normal-
mode registers contained within the design blocks. The normal mode registers are required for
normal operation.
10.7.1 Mapping and link identification
Within the clock/data interface, the external links are mapped to a contiguous space identified as
Virtual Links. To support multiple fractional TC flows on a single external signal, a mapping is
used to split a single channelized external signal into multiple Virtual Links. At the per-link
FIFOs, the clock/data Virtual Link naming convention is replaced 1:1 with the Physical Link
naming convention.
The S/UNI-IMA-4 processes 4 Physical Links, numbered 0 to 3. The Clock and Data Interface
uses 4 External Signal pins, which are mapped to 4 Virtual Links. The 4 streams to/from the
line interfaces are referred to a Physical Links elsewhere inside the device.
Clock/Data
Within the Clock and Data Interface, the external signals RSCLK/TSCLK and
RSDATA/TSDATA are identified by sequential numbers from 0 to 3.
Within the RCAS/TCAS, these 4 external signals are mapped to a contiguous space identified as
Virtual Links 0 through 3. To support multiple fractional TC flows on a single external signal,
RCAS/TCAS mapping is used to split a single channelized external signal into multiple Virtual
Links. At the per-link FIFOs, the RCAS/TCAS Virtual Link naming convention is replaced 1:1
with the Physical Link naming convention.
IMA
Within the IMA sublayer, mapping is performed between the physical link Ids and the Any-
PHY/UTOPIA L2 virtual PHY address. This mapping can be a one-to-one relationship as for
TC connections or it may be a many-to-one relationship as for an IMA group.
The physical link to Virtual PHY mapping is independent in the RX and TX directions.
The selection of the RX VPHY ID in Any-PHY or single port UTOPIA L2 mode is
unconstrained as this ID exists only as a prepend. In multiple port UTOPIA L2 mode, the RX
VPHY ID must be a unique value between 0 and 3 for each flow.
The selection of the TX VPHY ID is limited by the following rule:
Sꢀ All groups must have a unique value between 0 and 7.
Note:
Sꢀ The actual address used on the Any-PHY bus to access a particular channel is a combination of the
TX VPHY ID (bits 2:0), which TCAEN bit is set (bits 6:3), and the Tx Any-PHY Address Config
Reg(bits 15:7).
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2020889, Issue 2
91
PMC [ PMC-SIERRA, INC ]
