S/UNI-IMA-4 Telecom Standard Product Data Sheet
Released
Figure 28 TAP Controller Finite State Machine
TRSTB=0
Test-Logic-Reset
0
1
1
1
1
Run-Test-Idle
Select-IR-Scan
0
Select-DR-Scan
0
0
1
1
Capture-IR
0
Capture-DR
0
Shift-IR
1
Shift-DR
1
0
0
0
0
1
1
Exit1-IR
0
Exit1-DR
0
Pause-IR
1
Pause-DR
1
0
0
Exit2-IR
1
Exit2-DR
1
Update-IR
Update-DR
1
0
1
0
All transitions dependent on input TMS
Test-Logic-Reset
The test logic reset state is used to disable the TAP logic when the device is in normal mode
operation. The state is entered asynchronously by asserting input, TRSTB. The state is entered
synchronously regardless of the current TAP controller state by forcing input, TMS high for 5
TCK clock cycles. While in this state, the instruction register is set to the IDCODE instruction.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2020889, Issue 2
88
PMC [ PMC-SIERRA, INC ]
