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PM7348 参数 Datasheet PDF下载

PM7348图片预览
型号: PM7348
PDF下载: 下载PDF文件 查看货源
内容描述: [ATM/SONET/SDH IC, CMOS, PBGA324,]
分类和应用: ATM异步传输模式
文件页数/大小: 318 页 / 1736 K
品牌: PMC [ PMC-SIERRA, INC ]
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S/UNI-IMA-4 Telecom Standard Product Data Sheet  
Released  
The boundary scan architecture consists of a TAP controller, an instruction register with  
instruction decode, a bypass register, a device identification register, and a boundary scan  
register. The TAP controller interprets the TMS input and generates control signals to load the  
instruction and data registers. The instruction register with instruction decode block is used to  
select the test to be executed and/or the register to be accessed. The bypass register offers a  
single-bit delay from primary input, TDI to primary output, TDO. The device identification  
register contains the device identification code.  
The boundary scan register allows testing of board inter-connectivity. The boundary scan  
register consists of a shift register placed in series with device inputs and outputs. Using the  
boundary scan register, all digital inputs can be sampled and shifted out on primary output,  
TDO. In addition, patterns can be shifted in on primary input, TDI and forced onto all digital  
outputs.  
10.6.2 TAP Controller  
The TAP controller is a synchronous finite state machine clocked by the rising edge of primary  
input, TCK. All state transitions are controlled using primary input, TMS. The finite state  
machine is described below.  
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.  
Document No.: PMC-2020889, Issue 2  
87