S/UNI-IMA-4 Telecom Standard Product Data Sheet
Released
10.5 Line Side Physical Layer
10.5.1 TX Clock/Data (TCAS)
The S/UNI-IMA-4 supports up to 4 two-pin Clock/Data serial interfaces to interface with
standard framers. Each link is independent and has its own associated clock. To enable easier
support of CTC, a common clock is also supported using the CTSCLK pin. The S/UNI-IMA-4
responds to the active edge of each transmit clock by generating a single bit.
When the external framer needs to insert transmission overhead (such as framing bits) into the
data stream provided by the S/UNI-IMA-4, the framer is required to gap the transmit clock
provided to the S/UNI-IMA-4. This will prevent the S/UNI-IMA-4 from outputting data bits
during the overhead bit period(s).
The Transmit Channel Assigner block (TCAS) processes up to 4 virtual links. Data for all links
is sourced from a single byte-serial stream from the TC layer. For each link, the TCAS provides
a holding register. The TCAS also performs parallel-to-serial conversion to form a bit-serial
stream. When multiple links are in need of data, TCAS requests data from upstream blocks on a
fixed priority basis with link TSDATA[0] having the highest priority and link TSDATA[3] the
lowest.
Links containing a T1 or an E1 stream may be channelized. Data at each time-slot may be
assigned either: (1) to be sourced from the virtual link or (2) to be unassigned. This mechanism
of assigning timeslots enables support of fractional links. The link clock should only be active
during time-slots 1 to 24 of a T1 stream and inactive during the frame bit. Similarly, the clock is
only active during time-slots 1 to 31 of an E1 stream and inactive during the framing byte. The
first bit of time-slot 1 of a channelized link is identified by noting the absence of the clock and
its re-activation. With knowledge of the transmit link and time-slot identity, the TCAS performs
a table look-up to identify which timeslots are in use.
Links may also be unchannelized. In that case, all data bytes on that link belong to the virtual
link. The TCAS performs a table look-up to identify the link to which a data byte belongs using
only the outgoing link identity, as no time-slots are associated with unchannelized links. The
link clock is only active during bit-times containing data to be transmitted; it is inactive during
bit-times that are to be ignored by the downstream devices, such as framing and overhead bits.
10.5.2 Rx Clock/Data (RCAS)
The S/UNI-IMA-4 provides up to 4 two-pin Clock/Data serial interfaces for interconnecting to
T1/E1 framers. Each link is independent and has its own associated clock. For each link, the
data is sent through a serial to parallel conversion to form data bytes. The data bytes are
multiplexed, in byte serial format, for delivery to the TC layer. In the event where multiple
streams have accumulated a byte of data, multiplexing is performed on a fixed priority basis,
with link #0 having the highest priority and link #3 the lowest.
For the clock and data interface, the framer must gap the clock for all framing bits for T1 and
for the framing byte for E0.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2020889, Issue 2
84
PMC [ PMC-SIERRA, INC ]
