S/UNI-IMA-4 Telecom Standard Product Data Sheet
Released
Register 0x188: TCAS Link Disable Register
Bit
15
14:2
1:0
Type
R/W
Function
VLDIS
Unused
Default
0
X
0
R/W
DVLINK[1:0]
This register indicates a virtual link that is to be disabled (unprovisioned) while individual time-
slots are changed. This allows virtual links to either turn on or off at once instead of gradually
while each time-slot in the provisioning RAM is written.
DVLINK[1:0]
The disable virtual link bits (DVLINK[1:0]) indicate the virtual link to be disabled. If
VLDIS=1, all time-slots mapped to this virtual link will be forced unprovisioned, and the
value in FDATA[7:0] will be transmitted.
VLDIS
The virtual link disable bit (VLDIS) disables the virtual link in DVLINK[1:0]. When
VLDIS=1, all time-slots mapped to DVLINK[1:0] will be forced unprovisioned, and the
PROV bit of those time-slots will be ignored. When VLDIS=0, the virtual link's
provisioning state is set by the PROV bit.
Register 0x1C0 – 0x1C7: TCAS Link #0 to Link #3 Configuration
Bit
15:3
2
1
0
Type
Function
Unused
Reserved
E1
Default
X
0
0
0
R/W
R/W
R/W
CEN
This register configures the operational modes of transmit link #0 to link #3 (TSDATA[N] /
TSCLK[N]; where 0 ? N ? 3).
CEN
The channelize enable bit (CEN) configures link #N for channelized operation.
When CEN=1, TSCLK[N] must be gapped during the T1 framing bit or the E1 framing
byte. Thus, on the first rising edge of TSCLK[N] after the extended low period, a
downstream device can sample the MSB of timeslot one.
When CEN=0, Link #N is unchannelized, and the E1 register bit is ignored. TSCLK[N] can
be gapped during non-data bits, and all data bits are treated as a contiguous stream without
regard to timeslots.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2020889, Issue 2
147
PMC [ PMC-SIERRA, INC ]
