S/UNI-IMA-4 Telecom Standard Product Data Sheet
Released
Register 0x182: TCAS Indirect Link Data Register
Bit
15:9
8
7:2
1:0
Type
Function
Unused
PROV
Unused
VLINK[1:0]
Default
X
0
X
0
R/W
R/W
The TCAS Timeslot Provision RAM maps Virtual Links to either timeslots in a physical link or
to an entire physical link. It also provisions timeslots.
This register contains either: (1) the data read from the TCAS Timeslot Provision RAM after an
indirect read operation or (2) the data to be inserted into the TCAS Timeslot Provision RAM
during an indirect write operation.
VLINK[1:0]
VLINK[1:0] is the Virtual Link from which this TCAS LINK/TSLOT is mapped. Valid
values are 0x0 to 0x3. For proper operation, timeslots from multiple physical links cannot
be mapped to the same VLINK.
After an indirect read operation has been completed, VLINK[1:0] reports the virtual link
number read from the TCAS Timeslot Provision RAM. The Virtual Link number to be
written to the TCAS Timeslot Provision RAM in an indirect write operation must be set up
in this register before triggering the write. VLINK[1:0] reflects the value written until the
completion of a subsequent indirect read operation.
PROV
The indirect provision enable bit (PROV) reports the timeslot provision enable flag read
from the timeslot provision RAM after an indirect read operation has been completed. The
provision enable flag to be written to the timeslot provision RAM in an indirect write
operation must be set up in this register before triggering the write. When PROV is set high,
the current time-slot is assigned to the virtual link as indicated by VLINK[1:0]. When
PROV is set low, the time-slot does not belong to any virtual link. The transmit link data is
set to the contents of the Idle Time-slot Fill Data register. PROV reflects the last value read
or written until the completion of a subsequent indirect read operation.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2020889, Issue 2
144
PMC [ PMC-SIERRA, INC ]
