S/UNI-IMA-4 Telecom Standard Product Data Sheet
Released
BUSY
The indirect access status bit (BUSY) reports the progress of an indirect access. BUSY is
set high when this register is written to trigger an indirect access, and will stay high until the
access is complete. At which point, BUSY will be cleared (low). Alternatively, BUSY will
be set high when TCAS first comes out of reset until the RAM has been initialized. This
register should be polled to determine either: (1) when data from an indirect read operation
is available in the Indirect Data register or (2) when a new indirect write operation may
commence. Any indirect operation that is initiated while BUSY is still high will be
corrupted.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2020889, Issue 2
143
PMC [ PMC-SIERRA, INC ]
