S/UNI-IMA-4 Telecom Standard Product Data Sheet
Released
Register 0x184: TCAS Framing Bit Threshold
Bit
15:7
6:0
Type
Function
Unused
FTHRES[6:0]
Default
X
0x1F
R/W
This register contains the threshold used by the clock activity monitor to detect for framing
bits/bytes.
FTHRES[6:0]
The framing bit threshold bits (FTHRES[6:0]) contain the threshold used by the clock
activity monitor to detect the presence of framing bits. A counter in the clock activity
monitor increments at each REFCLK and is cleared by a rising edge of the TSCLK. When
the counter exceeds the threshold given by FTHRES[6:0], a framing bit/byte has been
detected. FTHRES[6:0] should be set as a function of the REFCLK period and the expected
gapping width of TSCLK during framing bits/bytes.
For E1 only device operation, the following equation should be used to determine the
acceptable range of values for FTHRES:
ꢁ
ꢀ
ꢀ
.
/
/
ꢁ
ꢀ
ꢀ
.
/
/
REFCLK.Freq
TSCLK.E1.Freq
REFCLK.Freq
TSCLK.E1.Freq
*1.5 ꢂ FTHRES ꢂ
*7
0
0
For T1 device operation and mixed T1 and E1 device operation (T1 requirements are more
rigorous), the following equation should be used to determine FTHRES:
!
"
#
1
ꢂ
ꢁ
ꢁ
.
/
/
REFCLK.Freq
RSCLK.T1.Freq
FTHRES W
*1.5 ꢀ 3
2
0
3
For example, for T1 or mixed T1 and E1, with a REFCLK.Freq = 19.44MHz, FTHRES[6:0]
= 15.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2020889, Issue 2
145
PMC [ PMC-SIERRA, INC ]
