Released
Datasheet
PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATM Traffic Management Device
6.4 QRT-QSE Interface Timing
Output timing delays assume a capacitive loading of 30 pF on SE_D_OUT(3:0,3:0) and 48 pF on
SE_SOC_OUT. Figure 62 shows the bit-level timing for the QRT..
Tctsu
Tsesu
Fseclk
SE_CLK
SE_D_IN(3:0,3:0), BP_ACK_IN(3:0)
SE_D_OUT(3:0,3:0), BP_ACK_OUT(3:0)
RX_CELL_START
Tseho
Tseq
Tctho
Tseq
SE_SOC_OUT
Figure 62. QRT Bit-Level Timing
Symbol
Fseclk**
Parameter
Signals
Min
Max
Unit
Frequency of SE_CLK
clock duty cycle
SE_CLK
SE_CLK
65.4
40
68
60
2
MHz
%
<10 KHz Jitter tolerance *
BP_ACK_IN(3:0), SE_SOC_IN(3:0)
clock
period
>10 KHz Jitter tolerance *
BP_ACK_IN(3:0), SE_SOC_IN(3:0)
0.35
clock
period
Tctsu
Control signal setup time
Control signal hold time
Setup time before SE_CLK
RX_CELL_START
RX_CELL_START
1.5
0
ns
ns
ns
Tctho
Tsesu*
SE_D_IN(3:0,3:0), SE_SOC_IN(3:0),
BP_ACK_IN(3:0)
4.0
Tseho*
Tseq
Hold time after SE_CLK
Output delay from SE_CLK
Output delay skew *
SE_D_IN(3:0,3:0), SE_SOC_IN(3:0),
BP_ACK_IN(3:0)
1.5
2.9
ns
ns
ns
SE_D_OUT(3:0,3:0),
BP_ACK_OUT(3:0), SE_SOC_OUT
10.0
1.3
SE_D_OUT(0,3:0) and SE_SOC_OUT
SE_D_OUT(1,3:0) and SE_SOC_OUT
SE_D_OUT(2,3:0) and SE_SOC_OUT
SE_D_OUT(3,3:0) and SE_SOC_OUT
Input delay skew *
SE_D_IN(0,3:0) and SE_SOC_IN(0)
SE_D_IN(1,3:0) and SE_SOC_IN(1)
SE_D_IN(2,3:0) and SE_SOC_IN(2)
SE_D_IN(3,3:0) and SE_SOC_IN(3)
3
ns
90
PMC [ PMC-SIERRA, INC ]
