Released
Datasheet
PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATM Traffic Management Device
Symbol
Parameter
Signals
AB_RAM_CLK
Min
Max
Units
Tcyc
Tch
Clock period
10
3
ns
ns
ns
ns
Clock high period
Clock low period
AB_RAM_CLK
AB_RAM_CLK
AB_RAM_AD(16:0)
Tcl
3
Tadrsu
(Read) Required data valid before clock
Adress setup time
2.6
Tadrh
(Read) Required data valid after clock
Address hold time
AB_RAM_AD(16:0)
1
ns
Trds
(Read) Required data valid before clock
(Read) Required data valid after clock
Write enable setup time
AB_RAM_AD(16:0)
AB_RAM_AD(16:0)
/AB_RAM_WE
3.5
1
Trdh
Twesu
Tweh
3.5
1
ns
ns
ns
ns
ns
ns
ns
ns
Write enable hold time
/AB_RAM_WE
Tadspsu
Tadsph
Tadvnsu
Tadvnh
Toesu
Toeh
Address status processor setup time
Address status processor hold time
Address advance setup time
Address advance hold time
/AB_RAM_ADSP
/AB_RAM_ADSP
/AB_RAM_ADV
/AB_RAM_ADV
/AB_RAM_OE
3.3
1
3.4
1
Output enable setup time
1.4
-1
Output enable hold time
/AB_RAM_OE
Figure 61 shows the AB RAM write timing.
1
2
3
4
5
ABRAM WRITE CYCLE
Tcyc
Tch
Tcl
ABR_RAM_CLK
Tadsph
Tadspsu
/ABR_RAM_ADSP
/ABR_RAM_OE
Tadrh
Tadrh
Tweh
Tadrsu
Tadrsu
ABR_RAM_AD(16:0)
Address
Data 1
Twesu
/ABR_RAM_WE
/ABR_RAM_ADV
Figure 61. AB RAM Write Timing
88
PMC [ PMC-SIERRA, INC ]
