Released
Datasheet
PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATM Traffic Management Device
4.3.10 Boundary Scan Signals
Table 18. Test Signals (8 Signal Pins)
Drive/Input Slew
Signal Name
Ball
Type
Description
Level
Rate
/JTAG_RESET
C4
In
CMOS
JTAG Reset is an active low, true asynchronous reset to the
JTAG controller.
JTAG_TCK
JTAG_TDI
B5
B4
In
In
CMOS
CMOS
Scan Test Clock is an independent clock used to drive the inter-
nal boundary scan test logic. Connect this signal to VDD
through a pull-up resistor.
Scan Test Data Input is the serial input for boundary scan test
data and instruction bits. Connect this signal to VDD through a
pull-up resistor.
JTAG_TDO
JTAG_TMS
B3
C5
Out
In
4 ma
Mod Scan Test Data Output is the serial output for boundary scan
test data.
CMOS
Scan Test Mode Select controls the operation of the boundary
scan test logic. Connect this signal to VDD through a pull-up
resistor.
/TEST_MODE
/SCAN_EN
D4
E7
In
In
CMOS
CMOS
N/A
This is a manufacturing test mode bit for manufacturing test. It
MUST be pulled up for functional mode on the board.
Scan Test Enable is used to enable the internal scan test logic.
Connect this signal to VDD through a pull-up resistor.
PROC_MON
T26
Out
N/A
Process Monitor is used for manufacturing test. It is connected
to a NAND tree that may be used for VIL/VIH testing.
73
PMC [ PMC-SIERRA, INC ]
