Released
Datasheet
PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATM Traffic Management Device
4.3.7 Receive Cell Buffer DRAMs
Table 14. Receive Cell Buffer RAM Interface Signals (49 Pins)
Drive/
Input Level
Slew
Rate
Signal Name
Ball
Type
Description
RX_DRAM_ADD(8:0)
J26, F28, K25, G28,
H26, J27, K26, J25,
K28
Out
5 ma
Mod RX DRAM Address Bits 8 to 0 are
part of the 9-bit SRAM address bus.
Note that TX_DRAM_ADD(8)
must be connected to the AutoPre-
charge pin.If DRAM_TYPE = 1
(refer to “RX_DRAM_TYPE” on
page 104) then connect
RX_DRAM_ADD(8) to the DRAM
autoprecharge pin, which should be
bit 10 of the DRAM address bus
RX_DRAM_DATA(31:0)
B23, E21, D22, B24,
B25, C23, E22, C24,
D23, B26, C25, D24,
B27, E24, C26, E23,
D25, C27, G25, B28,
E26, C28, E27, D27,
D28, F25, E28, G26,
F26, F29, F27, G27
Bidir
5 ma/CMOS
Mod Receive DRAM Data Bits 31 to 0
are part of the 32-bit SRAM data
bus.
RX_DRAM_CLK
J28
Out
8 ma
Fast
Receive DRAM Clock provides the
clock to the SDRAM.This signal
should be terminated with a series
resistor before connecting to the
RAM modules
DRAM_CKE
L25
Out
Out
5 ma
5 ma
Mod DRAM Clock Enable provides a
clock enable signal for RX_DRAM
and TX_DRAM
/RX_DRAM_CS(1:0)
H25, H28
Mod Receive DRAM Chip Select Bits 1 to
0 enable the SDRAMs. If
DRAM_TYPE = 1 (refer to
“RX_DRAM_TYPE” on page 104),
these are RX_DRAM_ADD(9:8).
RX_DRAM_BA
/RX_DRAM_RAS
/RX_DRAM_CAS
/RX_DRAM_WE
N25
K27
M25
H27
Out
Out
Out
Out
5 ma
5 ma
5 ma
5 ma
Mod Receive DRAM Bank Address
defines the bank to which the opera-
tion is addressed.
Mod Receive DRAM Row Address Strobe
is an active low signal that writes in
the row address.
Mod
Receive DRAM Column Address
Strobe is an active low signal that
writes in the column address.
Mod Receive DRAM Write Enable is an
active low signal that enables a
write into the synchronous DRAM.
NOTE: DQM (I/O mask enables) pins to the SGRAM need to be tied to logic 0.
69
PMC [ PMC-SIERRA, INC ]
