Released
Datasheet
PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATM Traffic Management Device
4.3.11 Miscellaneous Signals
Table 19. Miscellaneous Signals (3 Signal Pins)
Drive
/Input Level
Signal Name
Ball
Type
Slew
Description
SYSCLK
B16
In
CMOS
System Clock provides a high speed clock
input for the state machine and the mem-
ory interfaces.
/OE
D5
C3
In
CMOS
Output Enable is an active low signal that
enables all the outputs of the device. Set-
ting it high will tri-state all outputs except
PROCMON and disable all input pull up
resistors for in-circuit IDD tests.
/RESET
VDD
In
In
5V or LV TTL
Reset is an active low signal used to ini-
tialize or re-initialize the device.
SE_CLK must be present for the reset to
take effect.
A3, A5, A10, A11, A14,
A16, A19, A20, A27,
A29, B2, C1, C29, K1,
K29, L1, L29, P1, P29,
T1, V29, W1, W29, Y1,
Y29, AC29, AE5, AG1,
AH3, AH29, AJ1, AJ3,
AJ5, AJ10, AJ11, AJ14,
AJ16, AJ19, AJ20, AJ27,
AJ29, E5, E25, AE25
N/A
Supply voltage 3.3 ± 5% V.
VSS
A2, A4, A7, A8, A9,
A12, A15, A18, A21,
A22, A23, A25, A26,
A28, B1, B29, D1, D26,
D29, E1, E6, E29, G1,
G29, H1, H29, J1, J29,
L11, L13, L15, L17, L19,
M1, M29, N11, N13,
N15, N17, N19, R1, R11,
R13, R17, R19, R29,
T29, U11, U13, U15,
U17, U19, V1, W11,
W13, W15, W17, W19,
AA1, AA29, AB1, AB29,
AC1, AD5, AD25, AE1,
AE29, AF1, AF29,
In
N/A
Ground.
AG29, AH1, AH2, AH28,
AJ2, AJ4, AJ7, AJ8, AJ9,
AJ12, AJ15, AJ18, AJ21,
AJ22, AJ23, AJ25, AJ26,
AJ28
74
PMC [ PMC-SIERRA, INC ]
