Released
Datasheet
PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATM Traffic Management Device
4.3.8 Transmit Cell Buffer DRAMs
Table 15. Transmit Cell Buffers RAM Interface Signals (48 Pins)
Drive/
Input Level
Slew
Rate
Signal Name
Ball
Type
Description
TX_DRAM_ADD(8:0)
AG21, AF20, AE21,
AH20, AG22, AG20,
AH21, AE18, AE17
Out
5 ma
Mod Transmit DRAM Address Bits 8
to 0 are part of the 9-bit DRAM
address bus. Note that
TX_DRAM_ADD(8) must be
connected to the AutoPrecharge
pin. If DRAM_TYPE = 1 (refer
to “RX_DRAM_TYPE” on
page 104) then connect
TX_DRAM_ADD(8) to the
DRAM autoprecharge pin,
which should be bit 10 of the
DRAM address bus.
TX_DRAM_DATA(31:0)
AB25, AC27, AE28,
AD27, AC26, AD26,
AE27, AF28, AF27,
AC25, AG28, AE26,
AG27, AE23, AF26,
AF25, AH27, AG25,
AG26, AH26, AE24,
AH25, AF23, AF24,
AJ24, AG24, AG23,
AE22, AH22, AF21,
AH24, AE20
Bidir
5 ma/CMOS
Mod Transmit DRAM Data Bits 31
to 0 are part of the 32-bit
DRAM data bus.
TX_DRAM_CLK
AH18
Out
Out
8 ma
5 ma
Fast
Transmit DRAM Clock pro-
vides the clock to the
SDRAM.This signal should be
terminated with a series resistor
before connecting to the RAM
modules
/TX_DRAM_CS(1:0)
AH23, AF22
Mod Transmit DRAM Chip Select
Bits 1 and 0 select the SDRAM
devices. If DRAM_TYPE = 1
(refer to “RX_DRAM_TYPE”
on page 104), then these are
TX_DRAM_ADD(9:8).
TX_DRAM_BA
/TX_DRAM_RAS
/TX_DRAM_CAS
AF17
AG19
AF19
Out
Out
Out
5 ma
5 ma
5 ma
Mod Transmit DRAM Bank Address
defines the bank to which the
operation is addressed.
Mod Transmit DRAM Row Address
Strobe is an active low signal
that writes in the row address.
Mod Transmit DRAM Column
Address Strobe is an active low
signal that writes in the column
address.
70
PMC [ PMC-SIERRA, INC ]
