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PM73487 参数 Datasheet PDF下载

PM73487图片预览
型号: PM73487
PDF下载: 下载PDF文件 查看货源
内容描述: 622 Mbps的ATM流量管理设备 [622 Mbps ATM Traffic Management Device]
分类和应用: 异步传输模式ATM
文件页数/大小: 251 页 / 2936 K
品牌: PMC [ PMC-SIERRA, INC ]
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Released  
Datasheet  
PM73487 QRT  
PMC-Sierra, Inc.  
PMC-980618  
Issue 3  
622 Mbps ATM Traffic Management Device  
Run-Test-Idle:  
The run test/idle state is used to execute tests.  
Capture-DR:  
The capture data register state is used to load parallel data into the test data reg-  
isters selected by the current instruction. If the selected register does not allow  
parallel loads or no loading is required by the current instruction, the test register  
maintains its value. Loading occurs on the rising edge of TCK.  
Shift-DR:  
The shift data register state is used to shift the selected test data registers by one  
stage. Shifting is from MSB to LSB and occurs on the rising edge of TCK.  
Update-DR:  
The update data register state is used to load a test register’s parallel output latch.  
In general, the output latches are used to control the device. For example, for the  
EXTEST instruction, the boundary scan test register’s parallel output latches are  
used to control the device’s outputs. The parallel output latches are updated on  
the falling edge of TCK.  
Capture-IR:  
The capture instruction register state is used to load the instruction register with a  
fixed instruction. The load occurs on the rising edge of TCK.  
Shift-IR:  
The shift instruction register state is used to shift both the instruction register and  
the selected test data registers by one stage. Shifting is from MSB to LSB and  
occurs on the rising edge of TCK.  
Update-IR:  
The update instruction register state is used to load a new instruction into the  
instruction register. The new instruction must be scanned in using the Shift-IR  
state. The load occurs on the falling edge of TCK.  
The Pause-DR and Pause-IR states are provided to allow shifting through the test  
data and/or instruction registers to be momentarily paused.  
The TDO output is enabled during states Shift-DR and Shift-IR. Otherwise, it is  
tri-stated.  
Boundary Scan Instructions  
The following is a description of the standard instructions. Each instruction  
selects an serial test data register path between input, TDI, and output, TDO.  
BYPASS  
The bypass instruction shifts data from input TDI to output TDO with one TCK  
clock period delay. The instruction is used to bypass the device.  
EXTEST  
The external test instruction allows testing of the interconnection to other devices.  
When the current instruction is the EXTEST instruction, the boundary scan regis-  
ter is place between input TDI and output TDO. Primary device inputs can be  
sampled by loading the boundary scan register using the Capture-DR state. The  
sampled values can then be viewed by shifting the boundary scan register using  
207  
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