Released
Datasheet
PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATM Traffic Management Device
(Continued)
Description
Field (Bits)
AL_RAM_CONFIG
(9:8)
Defines the size of the SRAM used to store the address translation tables and a number of other tables.
The processor must know or determine the SRAM size. Then, the processor must inform the device of
the SRAM size by configuring this field. Initialize to the proper setting.
0h
AL_RAM = 64K × 16 SSRAM.
8K VI_VPI_TABLE (13 bits). Sum of VI and VP bits. Refer to section 9.2.1
“VI_VPI_TABLE” starting on page 175.
4K VCI_TABLE (12 bits). Refer to “VCI_TABLE” on page 176.
4K service table.
8K multicast input pointer FIFOs 2 × 8 × 512.
16K multicast cell output pointer FIFOs 2 × 8 × 32 × 32.
8K transmit cell buffer linked list (one-half of the PHY).
8K receive cell buffer linked list.
1h
AL_RAM = 128K × 16 SSRAM.
16K VI_VPI_TABLE (14 bits).
16K VCI_TABLE (14 bits).
4K service table.
16K multicast input pointer FIFOs 2 × 8 × 1K.
16K multicast cell output pointer FIFOs 2 × 8 × 32 × 32.
16K transmit cell buffer linked list.
16K receive cell buffer linked list.
2h
AL_RAM = 256K × 16 SSRAM.
32K VI_VPI_TABLE (15 bits).
32K VCI_TABLE (15 bits).
4K service table.
16K multicast cell output pointer FIFOs 2 × 8 × 32 × 32.
16K multicast input pointer FIFOs 2 × 8 × 2K.
16K or 32K transmit cell buffer linked list.
16K or 32K or 64K receive cell buffer linked list.
AL_RAM = 512K × 16 SSRAM.
3h
128K VI_VPI_TABLE (17 bits).
64K VCI_TABLE (16 bits).
4K service table.
32K multicast input pointer FIFOs 2 × 8 × 2K.
32K multicast cell output pointer FIFOs 2 × 8 × 32 × 64.
16K or 32K or 64K transmit cell buffer linked list.
16K or 32Kor 64K receive cell buffer linked list.
Resets to 0b.
Not used
(7:2)
Write with a 0 to maintain software compatibility with future versions.
CH_RAM_CONFIG Defines the size of the SRAM used by the channel tables. The processor must know or determine the
SRAM size. Then, the processor must inform the device of the SRAM size by configuring this field.
Initialize to the proper setting. This setting has no effect on the QRT operation, but it may in a future
QRT device version.
(1:0)
0h
CH_RAM = 32K × 32 SSRAM.
2K channels.
1h
CH_RAM = 64K × 32 SSRAM.
4K channels.
2h
3h
CH_RAM = 128K × 32 SSRAM.
8K channels.
CH_RAM = 256K × 32 SSRAM.
16K channels.
Resets to 0b.
105
PMC [ PMC-SIERRA, INC ]
