Released
Datasheet
PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATM Traffic Management Device
Field (Bits)
Description
If RS_RAM_BIST_CONTROL is set to 01b
RS_RAM_BIST_FAIL
(17)
0
1
RAM BIST memory test has PASSED.
RAM BIST memory test has FAILED.
If RS_RAM_BIST_CONTROL is set to 10b
0
1
RAM BIST controller test has FAILED.
RAM BIST controller test has PASSED.
Note: This bit must be cleared by writing a ‘0’ before executing the RAM_BIST
memory or controller tests.
Resets to 0b.
TS_RAM_BIST_FAIL
(16)
If TS_RAM_BIST_CONTROL is set to 01b
0
1
RAM BIST memory test has PASSED.
RAM BIST memory test has FAILED.
If TS_RAM_BIST_CONTROL is set to 10b
0
1
RAM BIST controller test has FAILED.
RAM BIST controller test has PASSED.
Note: This bit must be cleared by writing a ‘0’ before executing the RAM_BIST
memory or controller tests.
Resets to 0b.
Not used
(15:5)
Write with a 0 to maintain software compatibility with future versions.
TF_RAM_BIST_COMPLETE
(4)
0
1
TF_RAM_BIST memory test is in progress
TF_RAM_BIST memory test has completed
Resets to 0b.
RF_RAM_BIST_COMPLETE
(3)
0
1
RF_RAM_BIST memory test is in progress
RF_RAM_BIST memory test has completed
Resets to 0b.
VO_RAM_BIST_COMPLETE
(2)
0
1
VO_RAM_BIST memory test is in progress
VO_RAM_BIST memory test has completed
Resets to 0b.
RS_RAM_BIST_COMPLETE
(1)
0
1
RS_RAM_BIST memory test is in progress
RS_RAM_BIST memory test has completed
Resets to 0b.
TS_RAM_BIST_COMPLETE
(0)
0
1
TS_RAM_BIST memory test is in progress
TS_RAM_BIST memory test has completed
Resets to 0b.
109
PMC [ PMC-SIERRA, INC ]
