Released
Datasheet
PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATM Traffic Management Device
7.2 Microprocessor Ports Bit Definitions
7.2.1 REVISION
This register contains the device part number and revision.
Address: 0h (0h byte)
Type: Read-only
Format: Refer to the following table.
Field (Bits)
Description
Not used
(31:16)
Driven with a 0. Mask on reads to maintain compatibility with future versions.
Indicates the part number. Always returns 487h.
PART_TYPE
(15:4)
REVISION
(3:0)
Driven with a 1h to indicate the second QRT version.
7.2.2 RESET
Address: 1h (4h byte)
Type: Read/write
Format: Refer to the following table.
Field (Bits)
Description
Write with a 0 to maintain software compatibility with future versions.
Not used
(31:2)
HW_RESET
(1)
1
Resets the device to a state similar to that resulting from asserting the
/RESET pin, except the microprocessor registers are available. The internal
or external RAMs are not available. This allows the basic mode of the
device to be initialized before the I/O is enabled.
0
This reset is deasserted.
Resets to 1b.
SW_RESET
(0)
1
Resets the device, except for the microprocessor interface. The processor
may initialize all the registers and internal memories without the cell flow
while this is asserted. The switch fabric and UTOPIA interface are running,
but there is no cell flow.
0
Normal operation.
Resets to 1b.
101
PMC [ PMC-SIERRA, INC ]
