Released
Datasheet
PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATM Traffic Management Device
7.2.6 RAM BIST RESULT
Address: 5h (14h byte)
Type: Read/Write
Format: Refer to the following table.
Field (Bits)
Description
Not used
(31:21)
Write with a 0 to maintain software compatibility with future versions.
TF_RAM_BIST_FAIL
(20)
If TF_RAM_BIST_CONTROL is set to 01b
0
1
RAM BIST memory test has PASSED.
RAM BIST memory test has FAILED.
If TF_RAM_BIST_CONTROL is set to 10b
0
1
RAM BIST controller test has FAILED.
RAM BIST controller test has PASSED.
Note: This bit must be cleared by writing a ‘0’ before executing the RAM_BIST
memory or controller tests.
Resets to 0b.
RF_RAM_BIST_FAIL
(19)
If RF_RAM_BIST_CONTROL is set to 01b
0
1
RAM BIST memory test has PASSED.
RAM BIST memory test has FAILED.
If RF_RAM_BIST_CONTROL is set to 10b
0
1
RAM BIST controller test has FAILED.
RAM BIST controller test has PASSED.
Note: This bit must be cleared by writing a ‘0’ before executing the RAM_BIST
memory or controller tests.
Resets to 0b.
VO_RAM_BIST_FAIL
(18)
If VO_RAM_BIST_CONTROL is set to 01b
0
1
RAM BIST memory test has PASSED.
RAM BIST memory test has FAILED.
If VO_RAM_BIST_CONTROL is set to 10b
0
1
RAM BIST controller test has FAILED.
RAM BIST controller test has PASSED.
Note: This bit must be cleared by writing a ‘0’ before executing the RAM_BIST
memory or controller tests.
Resets to 0b.
108
PMC [ PMC-SIERRA, INC ]
