Released
Datasheet
PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATM Traffic Management Device
Field (Bits)
Description
TF Ram BIST control
(13:12)
00
01
Normal operation.
BIST memory test mode. RAM BIST controller will begin testing the TF
Ram. This value must be maintained until the RF_RAM_COMPLETE bit in
the BIST_RESULT register is ‘1’.
10
11
BIST controller test mode. Perform the controller error detector test. The
TF_RAM_BIST_FAIL bit will be set to ‘1’ at the end of this operation
Invalid control code. Do not use
Resets to 00b.
Not used
(11:10)
Write with a 0 to maintain software compatibility with future versions.
Reserved
(9)
Write with a 0 to maintain future software compatibility.
Resets to 0.
Reserved
(8)
Write with a 0 to maintain future software compatibility.
Resets to 0.
Not used
(7:6)
Write with a 0 to maintain software compatibility with future versions.
UTOP_LOOP
(5)
NOTE: For UT loopback, the device must be in OC_12C_MODE (refer to
“RX_OC_12C_MODE” on page 118), and the ATM_CLK in the QRT
must be synchronously derived from the SYSCLK.
1
0
Loopback cells from receive UTOPIA to transmit UTOPIA.
Normal operation.
Resets to 0b.
SF_LOOP
(4)
NOTE: For SF loopback, the device must not use randomization (set
DISABLE_RANDOMIZATION = 1; refer to
“DISABLE_RANDOMIZATION” on page 107) and turn off the complex
phase aligners (set CPA_OFF = 1; refer to “CPA_OFF” on page 107).
1
0
Loopback at the switch fabric interface.
Normal operation.
Resets to 0b.
Not used
(3:1)
Write with a 0 to maintain software compatibility with future versions.
Resets to 0.
Reserved
(0)
103
PMC [ PMC-SIERRA, INC ]
