Released
Datasheet
PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATM Traffic Management Device
7.2.3 TEST_CONFIG
Address: 2h (8h byte)
Type: Read/Write
Format: Refer to the following table.
Field (Bits)
Description
Write with a 0 to maintain software compatibility with future versions.
Not used
(31:22)
VO Ram BIST control
(21:20)
00
01
Normal operation.
BIST memory test mode. RAM BIST controller will begin testing the VO
Ram. This value must be maintained until the VO_RAM_COMPLETE bit
in the BIST_RESULT register is ‘1’.
10
11
BIST Controller test mode. Perform the controller error detector test. The
VO_RAM_BIST_FAIL bit will be set to ‘1’ at the end of this operation
Invalid control code. Do not use
Resets to 00b.
RS Ram BIST control
(19:18)
00
01
Normal operation.
BIST memory test mode. RAM BIST controller will begin testing the RS
Ram. This value must be maintained until the RS_RAM_COMPLETE bit in
the BIST_RESULT register is ‘1’.
10
11
BIST controller test mode. Perform the controller error detector test. The
RS_RAM_BIST_FAIL bit will be set to ‘1’ at the end of this operation
Invalid control code. Do not use
Resets to 00b.
TS Ram BIST control
(17:16)
00
01
Normal operation.
BIST memory test mode. RAM BIST controller will begin testing the TS
Ram. This value must be maintained until the TS_RAM_COMPLETE bit in
the BIST_RESULT register is ‘1’.
10
11
BIST controller test mode. Perform the controller error detector test. The
TS_RAM_BIST_FAIL bit will be set to ‘1’ at the end of this operation
Invalid control code. Do not use
Resets to 00b.
RF Ram BIST control
(15:14)
00
01
Normal operation.
BIST memory test mode. RAM BIST controller will begin testing the RF
Ram. This value must be maintained until the RF_RAM_COMPLETE bit in
the BIST_RESULT register is ‘1’.
10
11
BIST controller test mode. Perform the controller error detector test. The
RF_RAM_BIST_FAIL bit will be set to ‘1’ at the end of this operation
Invalid control code. Do not use
Resets to 00b.
102
PMC [ PMC-SIERRA, INC ]
