S/UNI®-JET Data Sheet
Released
Register 3A0H: PRGD Control
Bit
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
PDR[1]
PDR[0]
QRSS
PS
TINV
RINV
AUTOSYNC
MANSYNC
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
1
0
PDR[1:0]
The PDR[1:0] bits select the content of the four pattern detector registers (at addresses xACH
to xAFH) to be any one of the pattern receive registers, the error count holding registers, or
the bit count holding registers. The selection is shown in Table 25:
Table 25 PRGD Pattern Detector Register Configuration
PDR[1:0] PDR#1
PDR#2
PDR#3
PDR#4
00, 01
Pattern Receive (LSB)
Pattern Receive Pattern Receive
Error Count
Bit Count
Pattern Receive (MSB)
Error Count (MSB)
Bit Count(MSB)
10
11
Error Count (LSB)
Bit Count (LSB)
Error Count
Bit Count
QRSS
The QRSS bit enables the zero suppression feature required when generating the QRSS
sequence. When QRSS is a logic one, a one is forced in the TDATO stream when the
following 14 bit positions are all zeros. When QRSS is a logic zero, the zero suppression
feature is disabled.
PS
The PS bit selects the generated pattern. When PS is a logic one, a repetitive pattern is
generated. When PS is a logic zero, a pseudo-random pattern is generated.
The PS bit must be programmed to the desired setting before programming any other PRGD
registers, or the transmitted pattern may be corrupted. Any time the setting of the PS bit is
changed, the rest of the PRGD registers should be reprogrammed.
TINV
The TINV bit controls the logical inversion of the generated data stream. When TINV is a
logic one, the data is inverted. When TINV is a logic zero, the data is not inverted
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
237
PMC [ PMC-SIERRA, INC ]
