S/UNI®-JET Data Sheet
Released
Register 39BH: S/UNI-JET Miscellaneous
Bit
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
AISOOF
Reserved
TPRBS
Reserved
TCELL
LOC_RESET
FORCELOS
LINESYSCLK
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
LINESYSCLK
LINESYSCLK is used to select the high-speed system clock which the TDPR and RDLC
transmit and receive HDLC controllers use as a reference. If LINESYSCLK is set to logic
one, then the RDLC uses the receive line clock (RCLK[x]) and the TDPR uses the transmit
line clock (TICLK[x]) as its high-speed system reference clock respectively. If
LINESYSCLK is set to logic zero, the RDLC uses the receive ATM Utopia interface clock
(RFCLK) and the TDPR uses the transmit ATM Utopia interface clock (TFCLK) as its high-
speed system reference clock respectively.
The read/write access rate to the RDLC and TDPR are limited by their high-speed reference
clock frequency. Data and Configuration settings can be written into the TDPR at a maximum
rate equal to 1/8 of its high-speed reference clock frequency. Data and status indications can
be read from the TDPR at a maximum rate equal to 1/8 of its high-speed reference clock
frequency. Data and status indications can be read from the RDLC at a maximum rate equal
to 1/10 of its high-speed reference clock frequency.
Instantaneous variations in the high-speed reference clock frequencies (e.g. jitter in the
receive line clock) must be considered when determining the procedure used to read and
write the TDPR and RDLC Registers.
FORCELOS
FORCELOS is used to force a LOS condition on the transmit unipolar or bipolar data outputs
TPOS/TDATO[x] and TNEG[x]. When FORCELOS is logic one, the TPOS/TDATO[x] and
TNEG[x] outputs will be forced to logic zero. When FORCELOS is logic zero, the
TPOS/TDATO[x] and TNEG[x] outputs will operate normally.
LOC_RESET
LOC_RESET performs a software local reset of the corresponding quadrant of the S/UNI-
JET . When LOC_RESET is logic one, the corresponding quadrant of the S/UNI-JET is held
in a reset state. When LOC_RESET is logic zero, the quadrant is in normal operational mode.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
233
PMC [ PMC-SIERRA, INC ]
