S/UNI®-JET Data Sheet
Released
Register 3A1H: PRGD Interrupt Enable/Status
Bit
Type
R/W
R/W
R/W
R
R
R
R
R
Function
SYNCE
BEE
XFERE
SYNCV
SYNCI
BEI
Default
0
0
0
X
X
X
X
X
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
XFERI
OVR
SYNCE
The SYNCE bit enables the generation of an interrupt when the pattern detector changes
synchronization state. When SYNCE is set to logic one, the interrupt is enabled.
BEE
The BEE bit enables the generation of an interrupt when a bit error is detected in the receive
data. When BEE is set to logic one, the interrupt is enabled.
XFERE
The XFERE bit enables the generation of an interrupt when an accumulation interval is
completed and new values are stored in the receive pattern registers, the bit counter holding
registers, and the error counter holding registers. When XFERE is set to logic one, the
interrupt is enabled.
SYNCV
The SYNCV bit indicates the synchronization state of the pattern detector. When SYNCV is a
logic one the pattern detector is synchronized (the pattern detector has observed at least 32
consecutive error-free bit periods). When SYNCV is a logic zero, the pattern detector is out-
of-sync (the pattern detector has detected six or more bit errors in a 64 bit period window).
SYNCI
The SYNCI bit indicates that the detector has changed synchronization state since the last
time this register was read. If SYNCI is logic one, then the pattern detector has gained or lost
synchronization at least once. SYNCI is set to logic zero when this register is read.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
239
PMC [ PMC-SIERRA, INC ]
