S/UNI®-JET Data Sheet
Released
The LOC_RESET bit for quadrant 1 (Register 09BH) also resets the chip level Utopia bus.
While the LOC_RESET for quadrant 1 is set to logic one, the S/UNI-JET’s Utopia bus will
be held in a reset state, and will not function. In applications where the Utopia bus is
required, the LOC_RESET for quadrant 1 should not be permanently set to logic one.
TCELL
When the TCELL bit is a logic one, the TPOHFP/TFPO/TMFPO/TGAPCLK/TCELL pin
takes on the TCELL function, and pulses once for every transmitted cell (idle or unassigned).
Reserved
The reserved bit should be set to logic zero for proper operation.
TPRBS
register bit TPRBS is used to insert a pseudo-random binary sequence into the transmit
stream in place of other payload data. The exact nature of the PRBS is configurable through
the PRGD Registers (xA0H to xAFH).
Reserved
The reserved bit should be set to logic zero for proper operation.
AISOOF
The AISOOF bit allows the receive data output stream on RDATO to be forced to all 1’s
when the DS3, E3, or J2 FRMR loses frame. When AISOOF is set to logic one, RDATO[x]
will be forced to all 1’s when frame alignment is lost. When AISOOF is set to logic zero,
RDATO will continue to output raw data even when frame alignment is lost.
Note: AISOOF is only valid in framer-only mode (FRMRONLY=1, S/UNI-JET
Configuration 1 Register).
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
234
PMC [ PMC-SIERRA, INC ]
