S/UNI®-JET Data Sheet
Released
Register 39CH: S/UNI-JET FRMR LOF Status.
Bit
Type
R
R/W
R
R/W
R/W
R/W
R/W
R/W
Function
FRMLOF
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
0
X
0
0
0
0
0
FRMLOFE
FRMLOFI
J2SIGTHRU
Reserved
Reserved
Reserved
Reserved
FRMLOFI
The FRMLOFI bit shows that a transition has occurred on the FRMLOF state. When
FRMLOFI is logic one, the FRMLOF state has changed since the last read of this register.
The FRMLOFI bit is cleared whenever this register is read.
FRMLOFE
The FRMLOFE bit enables the generation of an interrupt due to a change in the FRMLOF
state. When FRMLOFE is a logic one, the interrupt is enabled.
FRMLOF
The FRMLOF bit shows the current state of the E3/T3 LOF or the J2 Extended LOF
indication (depending on which mode is enabled). When FRMLOF is logic one, the framer
has lost frame synchronization for greater than 1ms, 2ms, or 3ms depending on the setting of
the LOFINT[1:0] bits in the S/UNI-JET Receive Configuration Register.
J2SIGTHRU
The J2SIGTHRU bit allows the signaling bits in timeslot 97 and 98 on the TDATI stream to
pass transparently through the J2 TRAN. When J2SIGTHRU is logic one, timeslots 97 and 98
are passed transparently through from TDATI. When J2SIGTHRU is logic zero, timeslots 97
and 98 are sourced from the J2 TRAN TS97 Signaling and J2 TRAN TS98 Signaling
Registers.
If J2SIGTHRU is set to logic one and TPRBS (S/UNI-JET Miscellaneous Register) is also set
to logic one, the transmitted PRBS will continue through timeslots 97 and 98.
J2SIGTHRU is only valid in framer-only mode (FRMRONLY=1, S/UNI-JET Configuration
1 Register).
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
235
PMC [ PMC-SIERRA, INC ]
