S/UNI®-JET Data Sheet
Released
Register 399H: RBOC Interrupt Status
Bit
Type
R
R
R
R
R
R
R
R
Function
IDLI
FEACI
FEAC[5]
FEAC[4]
FEAC[3]
FEAC[2]
FEAC[1]
FEAC[0]
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
X
FEAC[5:0]
The FEAC[5:0] bits contain the received FEAC channel codes. The FEAC[5:0] bits are set to
all-ones ("111111") when no code has been validated.
FEACI
The FEACI bit is set to logic one when a new FEAC code is validated. The FEAC code value
is contained in the FEAC[5:0] bits. The FEACI bit position is set to logic zero when this
register is read.
IDLI
The IDLI bit is set to logic one when a validated FEAC code is removed. The FEAC[5:0] bits
are set to all-ones when the code is removed. The IDLI bit position is set to logic zero when
this register is read.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
231
PMC [ PMC-SIERRA, INC ]
