S/UNI®-JET Data Sheet
Released
Register 398H: RBOC Configuration/Interrupt Enable
Bit
Type
Function
Unused
Unused
Unused
Unused
Unused
IDLE
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
0
R/W
R/W
R/W
AVC
FEACE
0
0
FEACE
The FEACE bit enables the generation of an interrupt when a valid FEAC(FEAC) code is
detected. When a logic one is written to FEACE, the interrupt generation is enabled.
AVC
The AVC bit position selects the validation criterion used in determining a valid FEAC code.
When a logic zero is written to AVC, a FEAC code is validated when eight out of the last 10
received codes are identical. The FEAC code is removed when 2 out of the last 10 received
code do not match the validated code.
When a logic one is written to AVC, a FEAC code is validated when four out of the last five
received codes are identical. The FEAC code is removed when a single received FEACs does
not match the validated code.
IDLE
The IDLE bit enables the generation of an interrupt when a validated FEAC is removed.
When a logic one is written to IDLE, the interrupt generation is enabled.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
230
PMC [ PMC-SIERRA, INC ]
