PM7340 S/UNI-IMA-8
PRELIMINARY
INVERSE MULTIPLEXING OVER ATM
DATA SHEET
PMC-2001723
ISSUE 3
INVERSE MULTIPLEXING OVER ATM
Alternatively, the CTSCLK can be used instead of the TSCLK[n] to lock the
clocks of all the links together
13.3 Any-PHY/UTOPIA L2 Interfaces
While the following diagrams present representative waveforms, they are not an
attempt to unambiguously describe the interfaces. The Pin Description section is
intended to present the detailed pin behavior and constraints on use.
The following parameters apply to all Any-PHY/UTOPIA interface figures:
m = 7 for 8-bit mode, 15 for 16 bit mode
k = is a function of 8/16 bit mode and number of prepends selected.
13.3.1 UTOPIA L2 Transmit Slave Interface
Figure 33 gives an example of the functional timing of the transmit interface when
configured as a 31-port UTOPIA L2 compliant transmit slave. The interface
responds to the enabled addresses as defined by the register Transmit Cell
Available Enable by asserting the TCA corresponding to the addressed PHY
when it is capable of accepting a complete cell. As a result, the master selects
one of the S/UNI-IMA-8’s PHYs by presenting the PHY address again during the
last cycle TENB is high. If the device had not been selected, TSOC, TDAT[m:0],
and TPRTY would have remained high-impedance.
Figure 33 illustrates that a cell transfer may be paused by deasserting TENB.
The device is reselected by presenting the PHY’s address the last cycle TENB is
high to resume the transfer.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
290
PMC [ PMC-SIERRA, INC ]
