PM7340 S/UNI-IMA-8
PRELIMINARY
INVERSE MULTIPLEXING OVER ATM
DATA SHEET
PMC-2001723
ISSUE 3
INVERSE MULTIPLEXING OVER ATM
setting the PROV bit in the corresponding word of the receive channel provision
RAM in the RCAS block to low.
Figure 26
- Channelized T1 Receive Link Timing
RSCLK[n]
RSDATA[n]
B7 B8 F B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3
TS 24 TS 1 TS 2
The timing relationship of the receive clock (RSCLK[n]) and data (RSDATA[n])
signals of a channelized E1 link is shown in Figure 27. The receive data stream is
an E1 frame with a single framing byte (F1 to F8 in Figure 27) followed by octet
bound time-slots 1 to 31. RSCLK[n] is held quiescent during the framing byte.
The RSDATA[n] data bit (B1 of TS1) clocked in by the first rising edge of
RSCLK[n] after the framing byte is the most significant bit of time-slot 1. The
RSDATA[n] bit (B8 of TS31) clocked in by the last rising edge of RSCLK[n] before
the framing byte is the least significant bit of time-slot 31. In Figure 27, the
quiescent period is shown to be a low level on RSCLK[n]. A high level, effected
by extending the high phase of bit B8 of time-slot TS31, is equally acceptable. In
channelized E1 mode, RSCLK[n] can only be gapped during the framing byte. It
must be active continuously at 2.048 MHz during all time-slot bits. Time-slots can
be ignored by setting the PROV bit in the corresponding word of the receive
channel provision RAM in the RCAS block to low.
Figure 27
- Channelized E1 Receive Link Timing
RSCLK[n]
B8
B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4
B6 B7
TS 31
F1 F2 F3 F4 F5 F6 F7 F8
FAS / NFAS
RSDATA[n]
TS 1
TS 2
13.2 Transmit Link Output Timing
The timing relationship of the transmit clock (TSCLK[n]) and data (TSDATA[n])
signals of a unchannelized link is shown in Figure 28. The transmit data is viewed
as a contiguous serial stream. There is no concept of time-slots in an
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
287
PMC [ PMC-SIERRA, INC ]
