PM7340 S/UNI-IMA-8
PRELIMINARY
INVERSE MULTIPLEXING OVER ATM
DATA SHEET
PMC-2001723
ISSUE 3
INVERSE MULTIPLEXING OVER ATM
Figure 30
- Channelized T1 Transmit Link Timing w/ Clock gapped high
TSCLK[n]
TSDATA[n]
B7 B8
TS 24
B2 B3 B4 B5 B6 B7 B8 B1 B2 B3
B1
F
TS 1
TS 2
The timing relationship of the transmit clock (TSCLK[n]) and data (TSDATA[n])
signals of a channelized E1 link is shown in Figure 31. The transmit data stream
is an E1 frame with a single framing byte (FAS/NFAS in Figure 31) followed by
octet bound time-slots 1 to 31. TSCLK[n] is held quiescent during the framing
byte. The most significant bit of each time-slot is transmitted first (B1 in Figure
31). The least significant bit of each time-slot is transmitted last (B8 in Figure 31).
The TSDATA[n] bit (B8 of TS31) before the framing byte is the least significant bit
of time-slot 31. In Figure 31, the quiescent period is shown to be a low level on
TSCLK[n]. A high level, effected by extending the high phase of bit B8 of time-slot
31, is equally acceptable. In channelized E1 mode, TSCLK[n] can only be
gapped during the framing byte. It must be active continuously at 2.048 MHz
during all time-slot bits. Time-slots that are not provisioned to belong to any
channel − i.e., the PROV bit in the corresponding word of the transmit channel
provision RAM in the TCAS block is set low − transmit the contents of the Idle
Time-slot Fill Data register.
Figure 31
- Channelized E1 Transmit Link Timing w/ Clock gapped Low
TSCLK[n]
B8
B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4
TS 1 TS 2
B6 B7
TS 31
B1
TSDATA[n]
FAS / NFAS
Figure 32
- Channelized E1 Transmit Link Timing w/ Clock gapped How
TSCLK[n]
B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4
B1
B6 B7 B8
TS 31
TSDATA[n]
FAS / NFAS
TS 1
TS 2
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
289
PMC [ PMC-SIERRA, INC ]
