PM7340 S/UNI-IMA-8
PRELIMINARY
INVERSE MULTIPLEXING OVER ATM
DATA SHEET
PMC-2001723
ISSUE 3
INVERSE MULTIPLEXING OVER ATM
13.3.5 Any-PHY Receive Slave Interface
Figure 37 gives an example of the functional timing of the receive interface when
configured as an Any-PHY compliant receive slave. The interface responds to the
polling of address “IMA” (which matches the address defined by the Receive
Any-PHY/UTOPIA Config register) by asserting RPA when it is capable of
accepting a complete cell. The Any-PHY master repolls addresses until it
receives an asserted RPA. As a result, the master re-selects the same RADR
again during the last cycle RENB is high to initiate a transfer. Once transfer is
initiated, RENB will remain asserted until the last data is received.
Figure 37
- Any-PHY Receive Slave
1
2
3
4
5
6
7
8
9
10
Polling
Selection
RCLK
RADR[4:0]
1F
PHY-X
PHY-Z
1F
PHY-Y
1F
PHY-X
2 RCLK
PHY-Y
1F
PHY-Z
PHY-X
1F
PHY-Z
PHY-A
2 RCLK
PHY-X
RPA
PHY-Z
Data 0
2 to Max -1
RDAT[m:0], RPRTY
IMA Add
Data 1
RENB
RSX
RSOP
13.4 SDRAM Interface
The following three diagrams depict the timing for signals destined for the pins of
the SDRAM during the Activate-Read (with Auto-precharge), Activate-Write (with
Auto-precharge), and Auto-refresh command sequences and Power-Up and
Initialization Sequence. The cbcmd signal is not an actual signal; it merely
represents the memory access command formed by the combination of the
individual SDRAM control signals (e.g., cbcsb and cbrasb). Also note that
reads/writes of cell buffers are always done in bursts of eight words, with 4 bursts
per cells; the first and third bursts involve the even banks and the second and
fourth bursts involve the odd banks in the SDRAM.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
294
PMC [ PMC-SIERRA, INC ]
