PM7340 S/UNI-IMA-8
PRELIMINARY
INVERSE MULTIPLEXING OVER ATM
DATA SHEET
PMC-2001723
ISSUE 3
INVERSE MULTIPLEXING OVER ATM
13
FUNCTIONAL TIMING
This section shows the functional relationship between inputs and outputs. No
propagation delays are shown.
13.1 Receive Link Input Timing
The timing relationship of the receive clock (RSCLK[n]) and data (RSDATA[n])
signals of an unchannelized link is shown in Figure 25. The receive data is
viewed as a contiguous serial stream. There is no concept of time-slots in an
unchannelized link. Each eight bits is grouped together into a byte with arbitrary
alignment. The first bit received (B1 in Figure 25) is deemed the most significant
bit of an octet. The last bit received (B8) is deemed the least significant bit. Bits
that are to be processed by the S/UNI-IMA-8 are clocked in on the rising edge of
RSCLK[n]. Bits that should be ignored (X in Figure 25) are squelched by holding
RSCLK[n] quiescent. In Figure 25, the quiescent period is shown to be a low
level on RSCLK[n]. A high level, effected by extending the high phase of the
previous valid bit, is also acceptable. Selection of bits for processing is arbitrary
and is not subject to any byte alignment or frame boundary considerations.
Figure 25
RSCLK[n]
RSDATA[n]
- Unchannelized Receive Link Timing
B1 B2 B3 B4 X B5 X
X X B6 B7 B8 B1 X
The timing relationship of the receive clock (RSCLK[n]) and data (RSDATA[n])
signals of a channelized T1 link is shown in Figure 26. The receive data stream is
a T1 frame with a single framing bit (F in Figure 26) followed by octet bound time-
slots 1 to 24. RSCLK[n] is held quiescent during the framing bit. The RSDATA[n]
data bit (B1 of TS1) clocked in by the first rising edge of RSCLK[n] after the
framing bit is the most significant bit of time-slot 1. The RSDATA[n] bit (B8 of
TS24) clocked in by the last rising edge of RSCLK[n] before the framing bit is the
least significant bit of time-slot 24. In Figure 26, the quiescent period is shown to
be a low level on RSCLK[n]. A high level, effected by extending the high phase of
bit B8 of time-slot TS24, is equally acceptable. In channelized T1 mode,
RSCLK[n] can only be gapped during the framing bit. It must be active
continuously at 1.544 MHz during all time-slot bits. Time-slots can be ignored by
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
286
PMC [ PMC-SIERRA, INC ]
