PM7340 S/UNI-IMA-8
PRELIMINARY
INVERSE MULTIPLEXING OVER ATM
DATA SHEET
PMC-2001723
ISSUE 3
INVERSE MULTIPLEXING OVER ATM
unchannelized link. Each eight bits is grouped together into a byte with arbitrary
byte alignment. Octet data is transmitted from most significant bit (B1 in Figure
28) and ending with the least significant bit (B8 in Figure 28). Bits are updated on
the falling edge of TSCLK[n]. A transmit link may be stalled by holding the
corresponding TSCLK[n] quiescent. In Figure 28, bits B5 and B2 are shown to be
stalled for one cycle while bit B6 is shown to be stalled for three cycles. In Figure
28, the quiescent period is shown to be a low level on TSCLK[n]. A high level,
effected by extending the high phase of the previous valid bit, is also acceptable.
Gapping of TSCLK[n] can occur arbitrarily without regard to either byte or frame
boundaries.
Figure 28
- Unchannelized Transmit Link Timing
TSCLK[n]
TSDATA[n]
B1 B2 B3 B4 B5
B6
B7 B8 B1 B2
The timing relationship of the transmit clock (TSCLK[n]) and data (TSDATA[n])
signals of a channelized T1 link is shown in Figure 29. The transmit data stream
is a T1 frame with a single framing bit (F in Figure 29) followed by octet bound
time-slots 1 to 24. TSCLK[n] is held quiescent during the framing bit. The most
significant bit of each time-slot is transmitted first (B1 in Figure 29). The least
significant bit of each time-slot is transmitted last (B8 in Figure 29). The
TSDATA[n] bit (B8 of TS24) before the framing bit is the least significant bit of
time-slot 24. In Figure 29, the quiescent period is shown to be a low level on
TSCLK[n]. A high level, effected by extending the high phase of bit B8 of time-slot
TS24, is equally acceptable. In channelized T1 mode, TSCLK[n] can only be
gapped during the framing bit. It must be active continuously at 1.544 MHz during
all time-slot bits. Time-slots that are not provisioned to belong to any channel (the
PROV bit in the corresponding word of the transmit channel provision RAM in the
TCAS block set low) transmit the contents of the Idle Fill Time-slot Data register.
Figure 29
- Channelized T1 Transmit Link Timing w/ Clock gapped Low
TSCLK[n]
TSDATA[n]
B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3
TS 24 TS 1 TS 2
F
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
288
PMC [ PMC-SIERRA, INC ]
