PM7340 S/UNI-IMA-8
PRELIMINARY
INVERSE MULTIPLEXING OVER ATM
DATA SHEET
PMC-2001723
ISSUE 3
INVERSE MULTIPLEXING OVER ATM
Register 0x072: RTTC Indirect Link Data Register #1
Bit
Type
Function
Default
15:11
Unused
10
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LCDOOCDPASS
HCSPASS
UNASSPASS
IDLEPASS
DDSCR
Reserved
DDELIN
OOCDE
0
0
0
0
0
0
0
0
0
0
0
HCSE
FOVRE
LCDE
This register contains either: (1) data read from the Link provision RAM after an
indirect Link read operation or (2) data to be inserted into the Link provision RAM
in an indirect Link write operation.
The bits to be written to the Link provision RAM, in an indirect Link write
operation, must be set up in this register before triggering the write. The bits
reflect the value written until the completion of a subsequent indirect Link read
operation.
The reset state of the bits enables standard ATM cell processing as stipulated in
ITU-T Recommendation I.432.1
LCDE:
The LCDE bit enables the generation of an interrupt due to a change in the
LCD state. When LCDE is set to logic 1, the interrupt is enabled.
FOVRE:
The FOVRE bit enables the generation of an interrupt due to a FIFO overrun
error condition. When FOVRE is set to logic 1, the interrupt is enabled.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
129
PMC [ PMC-SIERRA, INC ]
