PM7340 S/UNI-IMA-8
PRELIMINARY
INVERSE MULTIPLEXING OVER ATM
DATA SHEET
PMC-2001723
ISSUE 3
INVERSE MULTIPLEXING OVER ATM
Register 0x070: RTTC Indirect Link Status
Bit
Type
Function
Default
15
14
13
12:7
6:5
4:0
R
R/W
R/W
LBUSY
LRWB
DRHCSE
Unused
Reserved
LINK[4:0]
0
0
0
0
0
0
R/W
R/W
This register provides the link number used to access the link-provision RAM of
the receive TC processor. Writing to this register triggers an indirect link-register
access.
LINK[4:0]:
The LINK[4:0] is used to specify the link to be configured or interrogated in
the indirect link access. Only 8 links are available. Valid values for the LINK
field may range from 0x0 to 0x7.
DRHCSE:
Disable Reset of the HCS Error Count (DRHCSE) disables automatic reset of
the HCS Error Counter (HCSERR). When the bit is set to logic 0, automatic
reset of the HCS Error Counter is enabled. If an indirect read is initiated (i.e.,
CRWBs written with logic 1) with DRHCSE logic 0, the HCS Error Counter is
reset to zero upon completion of the indirect read. When the DRHCSE bit is
set to logic 1, automatic reset of the HCS Error Counter is disabled.
An indirect read results in the interrupt status, as well as the HCSERR count,
being read (and possibly cleared). In this situation, the DRHCSE bit is useful
for separating interrupt processing from HCSERR count accumulation
because it can disable the HCSERR count reset when querying for interrupts.
LRWB:
The Link indirect access control bit (LRWB) selects between a configure
(write) or interrogate (read) access to the Link context RAM. Writing a logic 0
to LRWB triggers an indirect write operation. Data to be written is taken from
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
127
PMC [ PMC-SIERRA, INC ]
