PM7340 S/UNI-IMA-8
PRELIMINARY
INVERSE MULTIPLEXING OVER ATM
DATA SHEET
PMC-2001723
ISSUE 3
INVERSE MULTIPLEXING OVER ATM
Register 0x074: RTTC Indirect Link Data Register #2
Bit
Type
Function
Default
15:6
5
4
3
2
Unused
OOCDV
LCDV
OOCDI
HCSI
R
R
R
R
R
R
1
0
0
0
0
0
1
0
FOVRI
LCDI
This register contains data read from the Receive TC Processor Link provision
RAM after an indirect read operation.
LCDI:
The LCDI bit is set high when there is a change in the loss of cell delineation
(LCD) state. This bit is reset immediately after a read to this register.
FOVRI:
The FOVRI bit is set to logic 1 when a FIFO overrun occurs. This bit is reset
immediately after a read to this register.
HCSI:
The HCSI bit is set high when an HCS error is detected. This bit is reset
immediately after a read to this register.
OOCDI:
The OOCDI bit is set high when the logical Link enters or exits the SYNC
state. The OOCDV bit indicates whether the logical Link is in the SYNC state
or not. The OOCDI bit is reset immediately after a read to this register.
LCDV:
The LCDV bit gives the Loss of Cell Delineation state. When LCD is logic 1,
an out of cell delineation (OCD) defect has persisted for the number of cells
specified in the LCD Count Threshold register. When LCD is logic 0, no OCD
has persisted for the number of cells specified in the LCD Count Threshold
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
132
PMC [ PMC-SIERRA, INC ]
