PM7340 S/UNI-IMA-8
PRELIMINARY
INVERSE MULTIPLEXING OVER ATM
DATA SHEET
PMC-2001723
ISSUE 3
INVERSE MULTIPLEXING OVER ATM
Register 0x062: TTTC Indirect Link Data Register #1
Bit
Type
Function
Default
15:3
Unused
DHCS
Reserved
DSCR
0
0
0
0
2
1
0
R/W
R/W
R/W
This register contains either: (1) data read from the link-provision RAM of the
Transmit TC processor after an indirect Link read operation or (2) data to be
inserted into the link provision RAM in an indirect Link write operation.
DSCR:
The indirect scrambling disable bit (DSCR) configures scrambling. The
scramble disable bit to be written to the link provision RAM, in an indirect link
write operation, must be set up in this register before triggering the write.
When DSCR is logic 1, scrambling is disabled. When DSCR is logic 0, the 48
byte payload is scrambled. DSCR reflects the value written until the
completion of a subsequent indirect link-read operation.
DHCS:
The Disable HCS (Header Check Sequence) bit (DHCS) configures the
insertion of the HCS in the fifth byte of the cell. The value of DHCS to be
written to the link provision RAM, in an indirect link write operation, must be
set up in this register before triggering the write. When DHCS is logic 0, the
CRC-8 calculation over the first four bytes of the cell overwrites the fifth byte.
When DHCS is logic 1, the fifth byte of the cell passes through unmodified.
DHCS reflects the value written until the completion of a subsequent indirect
link-read operation.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
126
PMC [ PMC-SIERRA, INC ]
