PM7340 S/UNI-IMA-8
PRELIMINARY
INVERSE MULTIPLEXING OVER ATM
DATA SHEET
PMC-2001723
ISSUE 3
INVERSE MULTIPLEXING OVER ATM
11.5 TC Layer Registers
Register 0x060: TTTC Indirect Status
Bit
Type
Function
Default
15
14
13:7
6:5
4:0
R
R/W
LBUSY
LRWB
Unused
Reserved
LINK[4:0]
0
0
0
0
0
R/W
R/W
This register provides the link number used to access the link-provision RAM of
the transmit TC processor. Writing to this register triggers an indirect link register
access.
LINK[4:0],
The LINK[4:0] are used to specify the link to be configured or interrogated in
the indirect link access. Valid values for the LINK fieldshould range from 0x0
to 0x7.
LRWB:
The link indirect access control bit (LRWB) selects between either a configure
(write) or interrogate (read) access to the link-context RAM. Writing a logic 0
to LRWB triggers an indirect write operation. Data to be written is taken from
the Indirect Link Data registers. Writing a logic 1 to LRWB triggers an indirect
read operation. The read data can be found in the Indirect Link Data registers.
LBUSY:
The indirect link access status bit (LBUSY) reports the progress of an indirect
access A write to the Indirect Link Address register triggers an indirect access
and sets LBUSY to logic 1; it will remain logic 1 until the access is complete.
This register should be polled to determine either: (1) when data from an
indirect read operation is available in the Indirect Link Data registers or (2)
when a new indirect write operation may commence. The LBUSY is not
expected to remain at logic 1 for more than 86 REFCLK cycles.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
125
PMC [ PMC-SIERRA, INC ]
