PM7340 S/UNI-IMA-8
PRELIMINARY
INVERSE MULTIPLEXING OVER ATM
DATA SHEET
PMC-2001723
ISSUE 3
INVERSE MULTIPLEXING OVER ATM
HCSE:
The HCSE bit enables the generation of an interrupt due to the detection of
an HCS error. When HCSE is set to logic 1, the interrupt is enabled.
OOCDE:
The OOCDE bit enables the generation of an interrupt due to a change in the
cell delineation state. When OOCDE is set to logic 1, the interrupt is enabled.
DDELIN:
The indirect disable delineate enable bit (DDELIN) configures the TC
processor to perform cell delineation and header error detection on the
incoming data stream. When DDELIN is set to logic 0, the cell alignment is
established and maintained on the incoming data stream. When DDELIN is
set to logic 1, the RTTC does not perform any processing on the incoming
stream, but passes data through transparently.
DDSCR:
The DDSCR bit controls the descrambling of the cell payload with the
polynomial x43 + 1. When DDSCR is set to logic 1, cell payload descrambling
is disabled. When DDSCR is set to logic 0, payload descrambling is enabled.
IDLEPASS:
The IDLEPASS bit controls the function of the idle cell filter. When IDLEPASS
is written with a logic 0, all idle cells (i.e., the first four bytes of a cell: x00, x00,
x00, and x01) are filtered out. When IDLEPASS is logic 1, idle cells are
passed to the external cell buffer.
UNASSPASS:
When UNASSPASS is written with a logic 0, all unassigned cells (i.e., the first
four bytes of a cell: x00, x00, x00, and x00) are filtered out. When
UNASSPASS is logic 1, unassigned cells are passed to on the external cell
buffer.
HCSPASS:
The HCSPASS bit controls the dropping of cells based on the detection of an
HCS error. When HCSPASS is logic 0, cells containing an HCS error are
dropped. When HCSPASS is a logic 1, cells are passed to the external cell
buffer regardless of errors detected in the HCS.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
130
PMC [ PMC-SIERRA, INC ]
