PM7340 S/UNI-IMA-8
PRELIMINARY
INVERSE MULTIPLEXING OVER ATM
DATA SHEET
PMC-2001723
ISSUE 3
INVERSE MULTIPLEXING OVER ATM
Register 0x04A: SDRAM DIAG WRITE CMD 1
Bit
Type
Function
Default
15:0
R/W
WR_BUFFER_ADDR[15:0] 0
WR_BUFFER_ADDR[15:0]
Indicates the lower 16 bits of the addresses of the cell buffer to write. SDRAM
DIAG Write CMD 2 provides the upper address bit and triggers the burst
access to happen.
Register 0x04C: SDRAM DIAG WRITE CMD 2
Bit
Type
Function
Default
15
14:1
0
R
WRBUSY
Unused
WR_BUFFER_ADDR[16]
0
R/W
0
A write to the SDRAM DIAG WR_CMD 2 register will trigger a transfer of data
from the Write Burst Ram to the external SDRAM. The lower bits of the address
of the cell buffer in the external SDRAM are given in the SDRAM DIAG WRITE
CMD 1 register.
WR_BUFFER_ADDR[16]
Indicates the upper bit of the addresses of the cell buffer to write. SDRAM
DIAG Write CMD 1 provides the lower address bits.
WRBUSY
The Write Busy bit (WRBUSY) reports the progress of the write access to
SDRAM. WRBUSY is set high when this register is written; this triggers the
SDRAM access; it stays high until the access is complete. At which point,
WRBUSY will be set low. This register should be polled to determine when a
new diagnostic write operation may commence. While the WRBUSY bit is
set, no indirect accesses to the write burst ram should be performed.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
123
PMC [ PMC-SIERRA, INC ]
