S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
The S/UNI-ATLAS-3200 output interface must behave as the Rx PHY-layer on the POS-PHY
bus. As the PHY-layer, it controls the flow of information to the Link-layer. It does so by
selecting the channel for transfer on the data bus, RPP_DAT. Channel selection is performed in a
weighted round-robin fashion controlled by a software-configurable calendar. The calendar is
programmed via the RxPhy block’s Calendar Address and Data Register, and is described in
Section 10.1.7. When a PHY queue is serviced, it is permitted to transfer one ATM cell or POS-
PHY packet, or an amount of data equal to the Burst Size for that PHY, whichever is less. The
RxPhy block, assisted by the Output SDQ block (see below) performs the above functions. Its
configuration registers may be found in Section 11.9.
10.1.4 Egress Mode with POS_PHY Level 3 Signaling
In this configuration, the S/UNI-ATLAS-3200 receives traffic from a traffic manager, and
transmits traffic to a PHY. This traffic consists of variable-length packets, transferred using POS-
PHY Level 3 signaling.
Figure 8 POS-PHY Level 3 Egress Interface
SRAM Interface
JTAG
CELL FLOW
JTAG Interface
packets
cells
packets
cells
Packet Bypass
SDQ
Ingress Input:
UL3 master or
POS PHY link
layer interface
TPP_CLK
Ingress Output:
UL3 slave or
Cell Processor
TLP_CLK
TLP_ENB
TLP_DAT[31:0]
TLP_MOD[1:0]
TLP_PAR
TLP_SOP
TLP_EOP
TLP_ERR
TLP_SX
TPP_ENB
TPP_DAT[31:0]
TPP_MOD[1:0]
TPP_PAR
Policing, OAM,
POS PHY phy
layer interface
Statistics,
Translation
Egress Input:
UL3 slave or
Egress Output:
POS3
POS3
UL3 master or
POS PHY phy
TPP_SOP
TPP_EOP
TPP_ERR
TPP_SX
TPP_PTPA
TPP_STPA
POS PHY link
Tx Master
Tx Slave
layer interface
layer interface
Link Layer
PHY Layer
Interface
Connection Table
(Embedded
DRAM)
Interface
TLP_STPA
TLP_ADDR[5:0]
TLP_PTPA
TPP_ADDR[5:0]
Input
Output
Microprocessor
Cell Interface
(IMCIF)
Microprocessor
Cell Interface
(OMCIF)
SCI-PHY
Interface
SCI-PHY
Interface
CPU Interface
Backward Output Cell
Interface
Backward Input Cell
Interface
Microprocessor Interface
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
68
PMC [ PMC-SIERRA, INC ]
