S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
Figure 7 POS-PHY Level 3 Ingress Interface
SRAM Interface
JTAG
CELL FLOW
JTAG Interface
packets
cells
packets
cells
Packet Bypass
FIFO
Ingress Output:
UL3 slave or
Cell Processor
RLP_DAT[31:0]
RLP_MOD[1:0]
RLP_PAR
POS PHY phy
layer interface
Policing, OAM,
Statistics,
RPP_CLK
RPP_ENB
RPP_DAT[31:0]
RPP_MOD[1:0]
RPP_PAR
RPP_VAL
RPP_SOP
RPP_EOP
RPP_ERR
RPP_SX
Egress Input:
Translation
Egress Output:
POS3
RLP_VAL
RLP_SOP
RLP_EOP
RLP_ERR
RLP_SX
RLP_CLK
UL3 slave or
POS3
UL3 master or
POS PHY phy
Rx Slave
Rx Master
POS PHY link
layer interface
Link Layer
Interface
Phy Layer
layer interface
Connection Table
(Embedded
DRAM)
Interface
RLP_ENB
Input
Output
Microprocessor
Cell Interface
(IMCIF)
Microprocessor
Cell Interface
(OMCIF)
SCI-PHY
Interface
SCI-PHY
Interface
CPU Interface
Backward Output Cell
Interface
Backward Input Cell
Interface
Microprocessor Interface
The S/UNI-ATLAS-3200 input interface must behave as the Rx Link-layer on the POS-PHY bus.
As the Link-layer, its function is to accept information sent by the PHY-layer, which controls the
flow of data and the selection process. The Link-layer provides a back-pressure indication
(RLP_ENB) to prevent it from overflowing. The RxLink block can map external PHY addresses
to different internal PHY addresses via a user-programmable port map, as described in Section
10.1.6. The RxLink block, assisted by the SDQ block (see below) performs the above functions.
The RxLink configuration registers may be found in Section 11.9
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
67
PMC [ PMC-SIERRA, INC ]
