S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
MCD[31:0]
The MCD[31:0] contains the cell data destined to, or read from, the Microprocessor Cell
Interface.
For the cell extract FIFO, the EXTCA bit and associated maskable interrupt indicate that a
cell is available to be read. Alternatively, the assertion of the DMAREQ output signals the
presence of the cell. Reads of this register return the words of the cell starting with the first.
If necessary, the read pointer can be reset to the start of the current cell by setting the
RESTART bit. Alternatively, the read pointer can be reset to the start of the next cell by
setting the ABORT bit.
In a polled mode, the INSRDY register bit indicates that the microprocessor may write
another cell. For interrupt driven systems, the INSRDYI interrupt status bit and associated
maskable interrupt indicate that a cell may be written.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
174
PMC [ PMC-SIERRA, INC ]
