S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
STANDBY
The STANDBY bit disables Cell Processing to avoid passing corrupted cells while
initializing the S/UNI-ATLAS-3200. When STANDBY is a logic 1, the S/UNI-ATLAS-3200
makes all bus cycles available for external SRAM and internal DRAM access (i.e. micro
access to the search tree or context is given highest priority, and no other processing will
interrupt the SRAM and DRAM busses).
If the STANDBY bit is set while cell processing is in progress, the processing of cells
currently in the pipeline is completed, but no more cells are accepted.
Reserved
This bit should be programmed to logic 0 for proper operation.
BUSYPOL
The BUSYPOL bit sets the polarity of the BUSYB primary output. If BUSYPOL is a logic 0,
the BUSYB primary output is active low. If BUSYPOL is a logic 1, the BUSYB output is
active high.
SRAM_BUSY_EN
When this bit is logic 1, the BUSY signal from the S/UNI-ATLAS-3200 will be asserted
whenever the external SRAM is busy. When 0, the BUSY signal will not react to SRAM
activity.
DRAM_BUSY_EN
When this bit is logic 1 the BUSY signal from the S/UNI-ATLAS-3200 will be asserted
whenever the internal DRAM is busy. When 0 the BUSY signal will not react to DRAM
activity.
POS_UL3B
When POS_UL3B is logic 1, then the device uses POS-PHY Level 3 signaling. When
POS_UL3B is logic 0, the device uses UTOPIA Level 3 signaling. This bit defaults to logic 1
to ensure that all pins that can be inputs or outputs, power up as inputs.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
152
PMC [ PMC-SIERRA, INC ]
