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PM73123-PI 参数 Datasheet PDF下载

PM73123-PI图片预览
型号: PM73123-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 8 LINK CES / DBCES AAL1 SAR [8 LINK CES/DBCES AAL1 SAR]
分类和应用:
文件页数/大小: 364 页 / 2908 K
品牌: PMC [ PMC-SIERRA, INC ]
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RELEASED  
PM73123 AAL1GATOR-8  
DATASHEET  
PMC-2000097  
ISSUE 2  
8 LINK CES/DBCES AAL1 SAR  
In the sink direction, the UMUX waits until the SNK_INTF FIFO has a cell to  
send. Once the SNK_INTF FIFO has a cell to send, the UMUX polls the A1SP  
associated with the cell for availability. Once the A1SP has room for the cell, the  
UMUX reads the cell out of the SNK_INTF FIFO and places it in the A1SP FIFO.  
The UMUX also supports two forms of UTOPIA to UTOPIA loopback; global  
loopback, where all cells are looped, and VC based loopback, where only a  
specific VC is used to loopback cells. In global loopback all cells received by the  
UTOPIA block are sent back out onto the UTOPIA bus. Global loopback is  
enabled by setting the U2U_LOOP bit in the UI_COMN_CFG register. In VC  
based loopback mode, any cell received with a VC that matches the loopback  
VC is sent back out onto the UTOPIA bus. VC based loopback is enabled by  
setting the VCI_U2U_LOOP bit in the UI_COMN_CFG register. The loopback  
VC is programmable by writing the U2U_LOOP_VCI register. The 3-cell FIFO is  
used for loopback.  
9.2 AAL1 SAR Processing Block (A1SP)  
The A1SP block is the main AAL1 SAR processing block. This block processes  
8 E1/T1 lines. This block has the following major components.  
Transmit Frame Transfer Controller (TFTC) block  
Cell Service Decision (CSD) block  
Transmit Adaptation Layer Processor (TALP) block  
TALP FIFO (TFIFO) block  
Local Loopback Block (LOC_LPBK) block  
Receive Frame Transfer Controller (RFTC) block  
Receive Adaptation Layer Processor (RALP) block  
RALP FIFO (RFIFO) block  
Figure 6 shows a block diagram of the AAL1gator-8 and the sequence of events  
used to segment and reassemble the CBR data.  
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL  
73  
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