RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
5. Parameter tHAR is not applicable if address latching is used.
6. Read Timing is dependent upon the region read and the SYS_CLK
frequency. With a 40 MHZ SYS_CLK, Registers reads typically complete
within 70 ns. Internal memory table reads typically complete within 110 ns,
and external memory reads typically complete within 180ns to 200 ns.
However memory accesses can take up to 10 us if there is a lot of contention.
7. WRB must be high during reads.
Table 35 Microprocessor Interface Write Access
Symbol
Parameter
Min
Max
Units
TSAW
TSDW
TSALW
THALW
TVL
Address to Valid Write Set-up Time
Write active to Data Valid Set-up Time
Address to Latch Set-up Time
Address to Latch Hold Time
Valid Latch Pulse Width
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
10
10
5
TSLW
THLW
THDW
THAW
TPACKL
Latch to Write Set-up
0
Latch to Write Hold
5
Data to Valid Write Hold Time
Address to Valid Write Hold Time
5
5
Valid Write to Valid ACKB
Propagation Delay
3
400
20
SYS_
CLK
cycles
TZACKH
Valid Write Negated to Output Tri-
state
ns
* Microprocessor may momentarily experience excessive delays when
accessing the external SSRAM, but will average 10-15 SYSCLK cycles.
Microprocessor accesses to internal registers will not experience these
excessive delays.
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL
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